Description: Double port ROM verilog realization, based on the development of the Actel development platform based on Actel company development platform, verilog simultaneous fifo design
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File list (Check if you may need any files):
Syn_FIFO\SYN_FIFO\designer\impl1\designer.log
........\........\........\.....\FIFO_top.adb
........\........\........\.....\.........dtf\verify.log
........\........\........\.....\FIFO_top.ide_des
........\........\........\.....\FIFO_top.pdb
........\........\........\.....\FIFO_top.pdb.depends
........\........\........\.....\FIFO_top.tcl
........\........\........\.....\........_fp\$$FlashPro_FPBBALTLPT1.L$$
........\........\........\.....\...........\FIFO_top.log
........\........\........\.....\...........\FIFO_top.pro
........\........\........\.....\...........\projectData\FIFO_top.pdb
........\........\hdl\ctrl_FIFO.v
........\........\...\FIFO_top.v
........\........\...\rec.v
........\........\...\send.v
........\........\simulation\meminit.dat
........\........\..........\modelsim.ini
........\........\..........\modelsim.ini.sav
........\........\.martgen\smartgen.aws
........\........\........\.yn_fifo\syn_fifo.cxf
........\........\........\........\syn_fifo.gen
........\........\........\........\syn_fifo.log
........\........\........\........\syn_fifo.v
........\........\........\syn_fifo_work.ixf
........\........\.ynthesis\.recordref
........\........\.........\FIFO_top.areasrr
........\........\.........\FIFO_top.edn
........\........\.........\FIFO_top.fse
........\........\.........\FIFO_top.htm
........\........\.........\FIFO_top.map
........\........\.........\FIFO_top.sap
........\........\.........\FIFO_top.sdf
........\........\.........\FIFO_top.srd
........\........\.........\FIFO_top.srm
........\........\.........\FIFO_top.srr
........\........\.........\FIFO_top.srs
........\........\.........\FIFO_top.tlg
........\........\.........\FIFO_top_sdc.sdc
........\........\.........\FIFO_top_syn.prj
........\........\.........\stdout.log
........\........\.........\.yntmp\FIFO_top.msg
........\........\.........\......\FIFO_top.plg
........\........\.........\......\FIFO_top_flink.htm
........\........\.........\......\FIFO_top_srr.htm
........\........\.........\......\FIFO_top_toc.htm
........\........\.........\......\sap.log
........\........\.........\traplog.tlg
........\........\SYN_FIFO.prj
........\........\viewdraw\vf\project.lst
........\........\........\viewdraw.ini
........\Syn_FIFO_lab.rar
........\同步FIFO实验例程.pdf
........\SYN_FIFO\designer\impl1\FIFO_top_fp\projectData
........\........\........\.....\FIFO_top.dtf
........\........\........\.....\FIFO_top_fp
........\........\........\.....\simulation
........\........\........\impl1
........\........\smartgen\syn_fifo
........\........\.ynthesis\syntmp
........\........\viewdraw\sch
........\........\........\sym
........\........\........\vf
........\........\........\wir
........\........\component
........\........\constraint
........\........\coreconsole
........\........\designer
........\........\hdl
........\........\phy_synthesis
........\........\simulation
........\........\smartgen
........\........\stimulus
........\........\synthesis
........\........\viewdraw
........\SYN_FIFO
Syn_FIFO
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