Description: Complete digital clock fpga based design and implementation, the archive of the entire document, which zzz, zzz1, zzz2, zzz3 different top-level schematic case
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电子钟\CLOCK PCB ECO 2010-4-14 22-41-33.LOG
......\CLOCK PCB ECO 2010-4-14 22-55-58.LOG
......\CLOCK PCB ECO 2010-4-14 22-58-41.LOG
......\clock SCH ECO 2010-4-14 22-24-56.LOG
......\clock SCH ECO 2010-4-14 22-26-33.LOG
......\CLOCK.DRC
......\CLOCK.PCB3D
......\CLOCK.PcbDoc
......\clock.PrjPCB
......\clock.PrjPCBStructure
......\clock.SchDoc
......\clock.txt
......\DS12887.csv
......\DS12887.ERR
......\DS12887.rep
......\DS12887.SchLib
......\History\clock.~(1).#(AutoSave 2010-04-14 21~36~20-562).PrjPCB
......\.......\clock.~(1).#(AutoSave 2010-04-14 21~36~20-750).SchDoc
......\.......\CLOCK.~(1).PcbDoc
......\.......\clock.~(2).#(AutoSave 2010-04-14 22~06~20-968).PrjPCB
......\.......\clock.~(2).#(AutoSave 2010-04-14 22~06~21-171).SchDoc
......\.......\clock.~(3).#(AutoSave 2010-04-14 22~36~21-453).PrjPCB
......\.......\clock.~(3).#(AutoSave 2010-04-14 22~36~21-703).SchDoc
......\.......\clock.~(4).PrjPCB
......\.......\clock.~(4).SchDoc
......\.......\DS12887.~(1).SchLib
......\.......\DS12887.~(2).SchLib
......\.......\DS12887.~(3).#(AutoSave 2010-04-14 21~36~20-875).SchLib
......\.......\DS12887.~(4).#(AutoSave 2010-04-14 22~06~21-328).SchLib
......\.......\DS12887.~(5).#(AutoSave 2010-04-14 22~36~21-859).SchLib
......\Project Outputs for clock\clock.xls
......\.........................\Status Report.Txt
......\History
......\Project Outputs for clock
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