Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: Digital-stopwatch-design Download
 Description: Digital stopwatch design reports, using VHDL language programming, analysis and discussion of various functions to achieve, respectively, to compile and generate the corresponding module, and then connect these modules together to form a circuit, and compiled simulation.
 Downloaders recently: [More information of uploader 450335715]
 To Search:
File list (Check if you may need any files):
数字秒表的设计报告.doc
    

CodeBus www.codebus.net