AOI_CARD_0902\tbw_wr.tbw
.............\tbw_wr.jhd
.............\tbw_rd.udo
.............\tbw_wr.ant
.............\__ISE_repository_AOI_CARD_0902.ise_.lock
.............\AOI_CARD_0902.ise
.............\cpld.bld
.............\cpld.ngd
.............\tmperr.err
.............\cpld.rpt
.............\cpld.xml
.............\cpld_build.xml
.............\cpld.pad
.............\cpld_pad.csv
.............\cpld.vm6
.............\cpld.mfd
.............\cpld.nga
.............\cpld.gyd
.............\tbw_wr.udo
.............\AOI_CARD_0902.ise_ISE_Backup
.............\cpld.tspec
.............\cpld.tim
.............\tbw_wr_fit.prj
.............\xilinxsim.ini
.............\tbw_wr_isim_fit.exe
.............\isim.cmd
.............\isim.log
.............\results.txt
.............\isimwavedata.xwv
.............\isim.hdlsourcefiles
.............\cpld.ngr
.............\cpld.ngc
.............\cpld.stx
.............\tbw_wr.tdo
.............\transcript
.............\vsim.wlf
.............\tbw_rd.xwv
.............\cpld.lfp
.............\tbw_wr_bencher.prj
.............\tbw_rd_bencher.prj
.............\tbw_rd.xwv_bak
.............\tbw_rd.vhw
.............\tbw_rd.ant
.............\tbw_rd.tbw
.............\tbw_rd.jhd
.............\tbw_rd.tdo
.............\cpld.jed
.............\test_port.ucf
.............\test_port.lfp
.............\_pace.ucf
.............\cpld.pnx
.............\cpld.vhd
.............\cpld.prj
.............\cpld.xst
.............\.lso
.............\cpld.cmd_log
.............\cpld.syr
.............\cpld.lso
.............\pepExtractor.prj
.............\tbw_wr.xwv
.............\tbw_wr.xwv_bak
.............\xst\work\hdllib.ref
.............\...\....\hdpdeps.ref
.............\...\....\sub00\vhpl00.vho
.............\...\....\.....\vhpl01.vho
.............\work\_info
.............\....\tbw_rd\_primary.dat
.............\....\......\testbench_arch.dat
.............\....\......\testbench_arch.asm
.............\....\....wr\_primary.dat
.............\....\......\testbench_arch.dat
.............\....\......\testbench_arch.asm
.............\....\glbl\_primary.vhd
.............\....\....\verilog.asm
.............\....\....\_primary.dat
.............\....\cpld\_primary.vhd
.............\....\....\verilog.asm
.............\....\....\_primary.dat
.............\isim.tmp_save\_1
.............\....\simprim_ver.auxlib\hdllib.ref
.............\....\..................\_x___z_e_r_o\_x___z_e_r_o.h
.............\....\..................\............\mingw\_x___z_e_r_o.obj
.............\....\..................\.....x_o_r2\_x___x_o_r2.h
.............\....\..................\...........\mingw\_x___x_o_r2.obj
.............\....\..................\.....t_r_i\_x___t_r_i.h
.............\....\..................\..........\mingw\_x___t_r_i.obj
.............\....\..................\.....o_r2\_x___o_r2.h
.............\....\..................\.........\mingw\_x___o_r2.obj
.............\....\..................\.......p_a_d\_x___o_p_a_d.h
.............\....\..................\............\mingw\_x___o_p_a_d.obj
.............\....\..................\.......n_e\_x___o_n_e.h
.............\....\..................\..........\mingw\_x___o_n_e.obj
.............\....\..................\.....i_p_a_d\_x___i_p_a_d.h
.............\....\..................\............\mingw\_x___i_p_a_d.obj
.............\....\..................\.......n_v\_x___i_n_v.h
.............\....\..................\..........\mingw\_x___i_n_v.obj
.............\....\..................\.....f_f\_x___f_f.h
.............\....\..................\........\mingw\_x___f_f.obj
.............\....\..................\.....b_u_f\_x___b_u_f.h
.............\....\..................\..........\mingw\_x___b_u_f.obj