Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: rategy Download
 Description: FPGA board-level BIST design and implementation strategy
 Downloaders recently: [More information of uploader gu2046]
 To Search: bist
  • [dds] - Dds with vhdk signal generator written i
  • [BISTProject] - BIST test doing project, in verilog.
  • [uart] - UART design with bist capability
  • [fft] - fft of the FPGA implementation fft of th
File list (Check if you may need any files): 
基于FPGA的板级BIST设计和实现策略.pdf

CodeBus www.codebus.net