Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: alu Download
 Description: Arithmetic logic unit to achieve the program design, including: clear, logical multiplication, logical add, XOR, arithmetic plus, left, right, and so function
 Downloaders recently: [More information of uploader 1316215361]
 To Search:
File list (Check if you may need any files):
alu\alu.asm.rpt
...\alu.done
...\alu.eda.rpt
...\alu.fit.rpt
...\alu.fit.summary
...\alu.flow.rpt
...\alu.map.rpt
...\alu.map.summary
...\alu.merge.rpt
...\alu.pin
...\alu.qpf
...\alu.qsf
...\alu.qws
...\alu.sim.rpt
...\alu.tan.rpt
...\alu.tan.summary
...\alu.vhd
...\alu.vwf
...\alu_assignment_defaults.qdf
...\timing\primetime\alu.vho
...\......\.........\alu_pt_vhd.tcl
...\......\.........\alu_vhd.sdo
...\simulation\activehdl\alu.vho
...\..........\.........\alu_vhd.sdo
...\db\add_sub_ioh.tdf
...\..\add_sub_qph.tdf
...\..\alu.db_info
...\..\alu.eco.cdb
...\..\alu.sim.cvwf
...\..\alu.sld_design_entry.sci
...\..\wed.wsf
...\timing\primetime
...\simulation\activehdl
...\timing
...\simulation
...\db
alu
    

CodeBus www.codebus.net