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VHDL-FPGA-Verilog
Title:
rd_wr_generate
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Category:
VHDL-FPGA-Verilog
Tags:
[WORD]
File Size:
6kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
water_wzj
Description:
generate the address of reading and writing
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读写地址产生模块（rd_wr_generate）.doc
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