Description: Here is a Fifo impementation in vhdl with a 8 bit input and 8 bit output, reset and a synchronisation for reading and writing with different clocks
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v7\fifo.vhd
..\fifo_syn.vhdl
..\fifo_syn_tb.vhd
..\fifo_tb.vhd
..\mem.vhd
..\read_ptr.vhd
..\sync.vhd
..\up_cnt.vhd
..\write_ptr.vhd
v7
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