Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: VHDL-0.1s-Timer Download
 Description: The program completed the implementation in altera de2 0.1s under the new timer, which can be applied to the majority of sports events, a switch, pause start button, reset button.
 Downloaders recently: [More information of uploader yukeping]
 To Search:
File list (Check if you may need any files):
VHDL 0.1s Timer\db\DE2_Clock.db_info
...............\..\DE2_Clock.eco.cdb
...............\..\DE2_Clock.sld_design_entry.sci
...............\DE2_Clock.asm.rpt
...............\DE2_CLOCK.cdf
...............\DE2_Clock.done
...............\DE2_Clock.fit.eqn
...............\DE2_Clock.fit.rpt
...............\DE2_Clock.fit.summary
...............\DE2_Clock.flow.rpt
...............\DE2_Clock.map.eqn
...............\DE2_Clock.map.rpt
...............\DE2_Clock.map.summary
...............\DE2_Clock.pin
...............\DE2_Clock.qpf
...............\DE2_Clock.qsf
...............\DE2_Clock.qws
...............\DE2_CLOCK.sof
...............\DE2_Clock.tan.rpt
...............\DE2_Clock.tan.summary
...............\DE2_CLOCK.vhd
...............\DE2_CLOCK.vwf
...............\DE2_Clock_assignment_defaults.qdf
...............\db
VHDL 0.1s Timer
    

CodeBus www.codebus.net