Description: Design an 8-bit up and down synchronous counter in VHDL with the following features:
The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered.
The counter is with an asynchronous reset that assigns a specific initial value for counting.
The counter is with a synchronous data load control input for a new value of counting and an enable control input for allowing the up and down counting. The load control input has a priority over the enable control input. This implies that when the load operation is in process the counter operation is prohibited.
Some data types, such as STD_LOGIC, UNSIGNED, SIGNED and INTEGER, may be used.
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cnt8bc.txt
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