Description: `timescale 1ns/1ns
module asyn_fifo(clk_wr,wr_en,clk_rd,rd_en,rst,din,full,empty,dout)
input clk_wr,wr_en,clk_rd,rd_en,rst
input[7:0] din
output full,empty
output[7:0] dout
reg full_temp,empty_temp,full_temp1,empty_temp1
wire full,empty
wire[7:0] dout
reg[9:0] cnt_wr,cnt_rd,encode_cnt_wr,encode_cnt_rd
wire[9:0] gray_cnt_wr,gray_cnt_rd
integer i
reg[9:0] encode_a,encode_b,tempa,tempb
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