Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: FIR_matlab_verilog Download
 Description: using matlab to simulate a fir lowpass, then using verilog to implement it.
 Downloaders recently: [More information of uploader fengxd001]
 To Search: FIR_matlab_verilog fir matlab verilog
File list (Check if you may need any files): 
FIR_matlab_verilog\matlab\FIR.m
..................\......\hardware.m
..................\......\readme.txt
..................\rtl\fir_core.v
..................\...\tb.v
..................\matlab
..................\rtl
FIR_matlab_verilog

CodeBus www.codebus.net