cpu86\bin
.....\...\bin2case.exe
.....\...\bin2coe.exe
.....\...\bin2hex.exe
.....\...\bin2mem.exe
.....\copying.txt
.....\cpu86_rtl
.....\.........\alu_rtl.vhd
.....\.........\a_table.vhd
.....\.........\biufsm_fsm.vhd
.....\.........\biu_struct.vhd
.....\.........\cpu86instr.vhd
.....\.........\cpu86pack.vhd
.....\.........\cpu86_struct.vhd
.....\.........\datapath_struct.vhd
.....\.........\dataregfile_rtl.vhd
.....\.........\divider_rtl_ser.vhd
.....\.........\d_table.vhd
.....\.........\formatter_struct.vhd
.....\.........\ipregister_rtl.vhd
.....\.........\multiplier_rtl.vhd
.....\.........\m_table.vhd
.....\.........\n_table.vhd
.....\.........\proc_rtl.vhd
.....\.........\readme.txt
.....\.........\regshiftmux_regshift.vhd
.....\.........\r_table.vhd
.....\.........\segregfile_rtl.vhd
.....\drigmorn1
.....\.........\blk_mem_40K.mif
.....\.........\blk_mem_40K.ngc
.....\.........\coregen
.....\.........\.......\blk_mem_40K.asy
.....\.........\.......\blk_mem_40K.gise
.....\.........\.......\blk_mem_40K.ise
.....\.........\.......\blk_mem_40K.mif
.....\.........\.......\blk_mem_40K.ngc
.....\.........\.......\blk_mem_40K.sym
.....\.........\.......\blk_mem_40K.vhd
.....\.........\.......\blk_mem_40K.vho
.....\.........\.......\blk_mem_40K.xco
.....\.........\.......\blk_mem_40K.xise
.....\.........\.......\blk_mem_40Kx.vhd
.....\.........\.......\blk_mem_40K_flist.txt
.....\.........\.......\blk_mem_40K_readme.txt
.....\.........\.......\blk_mem_40K_xmdf.tcl
.....\.........\.......\coregen.cgp
.....\.........\.......\coregen.log
.....\.........\.......\coregen.zip
.....\.........\.......\MON88.COE
.....\.........\cpu86_summary.html
.....\.........\Drigmorn1.gise
.....\.........\DRIGMORN1.ucf
.....\.........\Drigmorn1.xise
.....\.........\drigmorn1_top_summary.html
.....\.........\Drigmorn1_xdb
.....\.........\.............\tmp
.....\.........\iseconfig
.....\.........\.........\Drigmorn1.projectmgr
.....\.........\.........\drigmorn1_top.xreport
.....\.........\isim.log
.....\.........\readme.txt
.....\.........\testbench
.....\.........\.........\Drigmorn1_tb.vhd
.....\.........\top_drigmorn1
.....\.........\.............\Bootstrap_rtl.vhd
.....\.........\.............\drigmorn1_top.vhd
.....\.........\.............\readme.txt
.....\.........\_xmsgs
.....\.........\......\pn_parser.xmsgs
.....\Modelsim
.....\........\loadfname.dat
.....\........\readme.txt
.....\........\run.bat
.....\........\tb.tcl
.....\........\wave.do
.....\Opencores
.....\.........\fileList.txt
.....\.........\LICENSE
.....\.........\README
.....\.........\readme.txt
.....\.........\slib_clock_div.vhd
.....\.........\slib_counter.vhd
.....\.........\slib_edge_detect.vhd
.....\.........\slib_fifo.vhd
.....\.........\slib_fifo_cyclone2.vhd
.....\.........\slib_input_filter.vhd
.....\.........\slib_input_sync.vhd
.....\.........\slib_mv_filter.vhd
.....\.........\uart_16750.vhd
.....\.........\uart_baudgen.vhd
.....\.........\uart_interrupt.vhd
.....\.........\uart_receiver.vhd
.....\.........\uart_transmitter.vhd
.....\readme.txt
.....\Software
.....\........\asm
.....\........\...\asm.bat
.....\........\...\hello.asm
.....\........\...\hello.hex