8255-testbench\bb_port_tb\bb_port.v
..............\..........\ghj.cr.mti
..............\..........\ghj.mpf
..............\..........\tb_bb_port.v
..............\..........\transcript
..............\..........\vsim.wlf
..............\..........\wave.do
..............\..........\.ork\_info
..............\..........\....\bb_port\verilog.asm
..............\..........\....\.......\_primary.dat
..............\..........\....\.......\_primary.vhd
..............\..........\....\tb_bb_port\verilog.asm
..............\..........\....\..........\_primary.dat
..............\..........\....\..........\_primary.vhd
..............\cc_port_testbench\cc_port.v
..............\.................\dfg.cr.mti
..............\.................\dfg.mpf
..............\.................\tb_cc_port.v
..............\.................\transcript
..............\.................\vsim.wlf
..............\.................\work\_info
..............\.................\....\cc_port\verilog.asm
..............\.................\....\.......\_primary.dat
..............\.................\....\.......\_primary.vhd
..............\.................\....\tb_cc_port\verilog.asm
..............\.................\....\..........\_primary.dat
..............\.................\....\..........\_primary.vhd
..............\inter_bus_buf_tb\inter_bus.v
..............\................\sdfr.cr.mti
..............\................\sdfr.mpf
..............\................\tb_inter_bus.v
..............\................\transcript
..............\................\vsim.wlf
..............\................\work\_info
..............\................\....\data_bus_buf\verilog.asm
..............\................\....\............\_primary.dat
..............\................\....\............\_primary.vhd
..............\................\....\inter_bus\verilog.asm
..............\................\....\.........\_primary.dat
..............\................\....\.........\_primary.vhd
..............\................\....\tb_inter_bus\verilog.asm
..............\................\....\............\_primary.dat
..............\................\....\............\_primary.vhd
..............\tb_top_8255\dfg.cr.mti
..............\...........\dfg.mpf
..............\...........\tb_top_8255.v
..............\...........\top_8255.v
..............\...........\transcript
..............\...........\vsim.wlf
..............\...........\work\_info
..............\...........\....\aa_port\verilog.asm
..............\...........\....\.......\_primary.dat
..............\...........\....\.......\_primary.vhd
..............\...........\....\bb_port\verilog.asm
..............\...........\....\.......\_primary.dat
..............\...........\....\.......\_primary.vhd
..............\...........\....\cc_port\verilog.asm
..............\...........\....\.......\_primary.dat
..............\...........\....\.......\_primary.vhd
..............\...........\....\data_bus_buf\verilog.asm
..............\...........\....\............\_primary.dat
..............\...........\....\............\_primary.vhd
..............\...........\....\inter_bus\verilog.asm
..............\...........\....\.........\_primary.dat
..............\...........\....\.........\_primary.vhd
..............\...........\....\r_w_con\verilog.asm
..............\...........\....\.......\_primary.dat
..............\...........\....\.......\_primary.vhd
..............\...........\....\tb_top_8255\verilog.asm
..............\...........\....\...........\_primary.dat
..............\...........\....\...........\_primary.vhd
..............\...........\....\.op_8255\verilog.asm
..............\...........\....\........\_primary.dat
..............\...........\....\........\_primary.vhd
....源代码\8255A的模块划分.doc
..........\aa_port.v
..........\bb_port.v
..........\cc_port.v
..........\data_bus_buf.v
..........\inter_bus.v
..........\P8255A.pdf
..........\r_w_con.v
..........\top_8255.v
..........\~$55A的模块划分.doc
..........\8255源代码\top_8255.v
..........\..........\说明.txt
....-quantus\cc_port\cc_port.asm.rpt
............\.......\cc_port.done
............\.......\cc_por