Description: H.264 decoder, written with verilog, can be achieved in the FPGA on the baseline of 264 decoding
File list (Check if you may need any files):
.\trunk
.\.....\test
.\.....\....\bitstream
.\.....\....\.........\akiyo300_1ref.txt
.\.....\....\readme.txt
.\.....\....\hex2bin.cpp
.\.....\....\bin2hex.pl
.\.....\MISC
.\.....\....\readme.txt
.\.....\src
.\.....\...\BitStream_parser_FSM_gating.v
.\.....\...\rec_gclk_gen.v
.\.....\...\DF_pipeline.v
.\.....\...\ram_async_1r_sync_1w.v
.\.....\...\cavlc_decoder.v
.\.....\...\bitstream_gclk_gen.v
.\.....\...\ext_RAM_ctrl.v
.\.....\...\Inter_pred_CPE.v
.\.....\...\timescale.v
.\.....\...\NumCoeffTrailingOnes_decoding.v
.\.....\...\pc_decoding.v
.\.....\...\exp_golomb_decoding.v
.\.....\...\ext_frame_RAM1_wrapper.v
.\.....\...\nova_tb.v
.\.....\...\CodedBlockPattern_decoding.v
.\.....\...\Inter_mv_decoding.v
.\.....\...\dependent_variable_decoding.v
.\.....\...\ext_frame_RAM0_wrapper.v
.\.....\...\end_of_blk_decoding.v
.\.....\...\hybrid_pipeline_ctrl.v
.\.....\...\level_decoding.v
.\.....\...\bs_decoding.v
.\.....\...\ram_sync_1r_sync_1w.v
.\.....\...\IQIT.v
.\.....\...\reconstruction.v
.\.....\...\QP_decoding.v
.\.....\...\DF_reg_ctrl.v
.\.....\...\Intra_pred_reg_ctrl.v
.\.....\...\nova.v
.\.....\...\run_decoding.v
.\.....\...\Inter_pred_pipeline.v
.\.....\...\Inter_pred_reg_ctrl.v
.\.....\...\Intra4x4_PredMode_decoding.v
.\.....\...\Intra_pred_pipeline.v
.\.....\...\nova_defines.v
.\.....\...\Inter_pred_LPE.v
.\.....\...\Inter_pred_top.v
.\.....\...\Beha_BitStream_ram.v
.\.....\...\BitStream_buffer.v
.\.....\...\Inter_pred_sliding_window.v
.\.....\...\total_zeros_decoding.v
.\.....\...\BitStream_controller.v
.\.....\...\Intra_pred_PE.v
.\.....\...\syntax_decoding.v
.\.....\...\nC_decoding.v
.\.....\...\sum.v
.\.....\...\DF_mem_ctrl.v
.\.....\...\Intra_pred_top.v
.\.....\...\heading_one_detector.v
.\.....\...\cavlc_consumed_bits_decoding.v
.\.....\...\DF_top.v
.\.....\...\rec_DF_RAM_ctrl.v
.\.....\doc
.\.....\...\nova_spec.doc
.\.....\...\readme.txt
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