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Title: 801332_code Download
 Description: impelement of transition bewteen pc and fpga through usb
 Downloaders recently: [More information of uploader rikkiluck777]
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写FIFO\写FIFO\Apptest\ezusbsys.h
......\......\.......\ReadMe.txt
......\......\.......\..lease\StdAfx.obj
......\......\.......\.......\Test.exe
......\......\.......\.......\Test.obj
......\......\.......\.......\Test.res
......\......\.......\.......\TestDlg.obj
......\......\.......\.......\vc60.idb
......\......\.......\.......\ 5- 1-18-10-13.bin
......\......\.......\.......\ 5- 1-18-21-17.bin
......\......\.......\.......\ 5- 1-18-25-17.bin
......\......\.......\.......\ 5- 1-18-27-11.bin
......\......\.......\.......\Test.pch
......\......\.......\res\cursor1.cur
......\......\.......\...\icon5.ico
......\......\.......\...\Test.ico
......\......\.......\...\Test.rc2
......\......\.......\...\usb.ico
......\......\.......\Resource.h
......\......\.......\StdAfx.cpp
......\......\.......\StdAfx.h
......\......\.......\Test.aps
......\......\.......\Test.clw
......\......\.......\Test.cpp
......\......\.......\Test.dsp
......\......\.......\Test.dsw
......\......\.......\Test.h
......\......\.......\Test.ncb
......\......\.......\Test.plg
......\......\.......\Test.rc
......\......\.......\TestDlg.cpp
......\......\.......\TestDlg.h
......\......\.......\ 5-11-11-56-13.bin
......\......\.......\ 5-11-11-56-24.bin
......\......\.......\Test.opt
......\......\wr_fifo\cmp_state.ini
......\......\.......\db\cntr_l18.tdf
......\......\.......\..\cntr_n28.tdf
......\......\.......\..\wr_fifo.cmp.logdb
......\......\.......\..\wr_fifo.asm.qmsg
......\......\.......\..\wr_fifo.cmp.bpm
......\......\.......\..\wr_fifo.tan.qmsg
......\......\.......\..\wr_fifo.cmp.cdb
......\......\.......\..\wr_fifo.signalprobe.cdb
......\......\.......\..\wr_fifo.cmp.tdb
......\......\.......\..\wr_fifo.cmp.hdb
......\......\.......\..\wr_fifo.eco.cdb
......\......\.......\..\wr_fifo.cmp.ecobp
......\......\.......\..\wr_fifo.root_partition.cmp.logdb
......\......\.......\..\wr_fifo.root_partition.cmp.dfp
......\......\.......\..\wr_fifo.tis_db_list.ddb
......\......\.......\..\wr_fifo.cmp.rdb
......\......\.......\..\wr_fifo.cmp0.ddb
......\......\.......\..\wr_fifo.sld_design_entry.sci
......\......\.......\..\wr_fifo_cmp.qrpt
......\......\.......\..\wr_fifo.db_info
......\......\.......\..\wr_fifo.cbx.xml
......\......\.......\..\wr_fifo.map_bb.hdbx
......\......\.......\..\prev_cmp_wr_fifo.qmsg
......\......\.......\..\wr_fifo.hif
......\......\.......\..\wr_fifo.hier_info
......\......\.......\..\wr_fifo.psp
......\......\.......\..\wr_fifo.syn_hier_info
......\......\.......\..\wr_fifo.root_partition.map.atm
......\......\.......\..\wr_fifo.root_partition.map.hdbx
......\......\.......\..\wr_fifo.map.ecobp
......\......\.......\..\wr_fifo.root_partition.cmp.rcf
......\......\.......\..\wr_fifo.root_partition.cmp.hdbx
......\......\.......\..\wr_fifo.root_partition.cmp.atm
......\......\.......\..\wr_fifo.tmw_info
......\......\.......\..\prev_cmp_wr_fifo.map.qmsg
......\......\.......\..\prev_cmp_wr_fifo.fit.qmsg
......\......\.......\..\prev_cmp_wr_fifo.asm.qmsg
......\......\.......\..\prev_cmp_wr_fifo.tan.qmsg
......\......\.......\..\wr_fifo.map.qmsg
......\......\.......\..\wr_fifo.rtlv_sg.cdb
......\......\.......\..\wr_fifo.rtlv.hdb
......\......\.......\..\wr_fifo.rtlv_sg_swap.cdb
......\......\.......\..\wr_fifo.pre_map.hdb
......\......\.......\..\wr_fifo.pre_map.cdb
......\......\.......\..\wr_fifo.root_partition.map.info
......\......\.......\..\wr_fifo.smp_dump.txt
......\......\.......\..\wr_fifo.map_bb.logdb
......\......\.......\..\wr_fifo.sgdiff.cdb
......\......\.......\..\wr_fifo.sgdiff.hdb
......\......\.......\..\wr_fifo.sld_design_entry_dsc.sci
......\......\.......\..\wr_fifo.map_bb.cdb
......\......\.......\..\wr_fifo.map_bb.hdb
......\......\.......\..\wr_fifo.map.cdb
......\......\.......\..\wr_fifo.map.hdb
......\......\.......\..\wr_fifo.map.logdb
......\......\.......\..\wr_fifo.map.bpm
......\......\.......\..\wr_fifo.fit.qmsg
......\......\.......\transcript
......\......\.......\vish_stacktrace.vstf
......\......\.......\vsim.wlf
......\......\.......\work\wr_fifo\verilog.asm
......\......\.......\...

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