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Title: x3cs400_uart Download
 Description: UART communication program based on X3CS400 FPGA, develop enviroment: ISE7.0,completed by verilog。 The result could be seen on the Uart debug assitant.
 Downloaders recently: [More information of uploader htons]
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Project\uart_rs232\.ram_dataout.v.swo
.......\..........\.ram_dataout.v.swp
.......\..........\.rs232.v.swp
.......\..........\.untf
.......\..........\automake.log
.......\..........\bitgen.ut
.......\..........\Block.xco
.......\..........\clk_div.xaw
.......\..........\clk_div_arwz.ucf
.......\..........\core.tpl
.......\..........\modelsim.ini
.......\..........\ram_dataout.asy
.......\..........\ram_dataout.edn
.......\..........\ram_dataout.ngo
.......\..........\ram_dataout.sym
.......\..........\ram_dataout.v
.......\..........\ram_dataout.veo
.......\..........\ram_dataout.vhd
.......\..........\ram_dataout.vho
.......\..........\ram_dataout.xco
.......\..........\ram_dataout_flist.txt
.......\..........\ram_dataout_readme.txt
.......\..........\rs232.bgn
.......\..........\rs232.bit
.......\..........\rs232.bld
.......\..........\rs232.cmd_log
.......\..........\rs232.drc
.......\..........\rs232.lfp
.......\..........\rs232.lso
.......\..........\rs232.mrp
.......\..........\rs232.nc1
.......\..........\rs232.ncd
.......\..........\rs232.ngc
.......\..........\rs232.ngd
.......\..........\rs232.ngm
.......\..........\rs232.ngr
.......\..........\rs232.pad
.......\..........\rs232.pad_txt
.......\..........\rs232.par
.......\..........\rs232.pcf
.......\..........\rs232.placed_ncd_tracker
.......\..........\rs232.prj
.......\..........\rs232.routed_ncd_tracker
.......\..........\rs232.stx
.......\..........\rs232.syr
.......\..........\rs232.twr
.......\..........\rs232.twx
.......\..........\rs232.ucf
.......\..........\rs232.ucf.untf
.......\..........\rs232.ut
.......\..........\rs232.v
.......\..........\rs232.xpi
.......\..........\rs232_cclktemp.bit
.......\..........\rs232_last_par.ncd
.......\..........\rs232_map.ncd
.......\..........\rs232_map.ngm
.......\..........\rs232_pad.csv
.......\..........\rs232_pad.txt
.......\..........\rs232_summary.html
.......\..........\rs232_test.v
.......\..........\rs232_test_v.fdo
.......\..........\rs232_test_v.udo
.......\..........\rs232_vhdl.prj
.......\..........\simprims_ver\_info
.......\..........\testbench.fdo
.......\..........\testbench.udo
.......\..........\transcript
.......\..........\txmit_test_v.fdo
.......\..........\txmit_test_v.udo
.......\..........\uart_rs232.dhp
.......\..........\uart_rs232.ipf
.......\..........\uart_rs232.ise
.......\..........\uart_rs232.ise_ISE_Backup
.......\..........\uart_summary.html
.......\..........\.ni9000\_info
.......\..........\...sims\_info
.......\..........\Untitled.mcs
.......\..........\Untitled.prm
.......\..........\Untitled.sig
.......\..........\vsim.wlf
.......\..........\work\clk_div\verilog.asm
.......\..........\....\.......\_primary.dat
.......\..........\....\.......\_primary.vhd
.......\..........\....\glbl\verilog.asm
.......\..........\....\....\_primary.dat
.......\..........\....\....\_primary.vhd
.......\..........\....\ram_dataout\verilog.asm
.......\..........\....\...........\_primary.dat
.......\..........\....\...........\_primary.vhd
.......\..........\....\.cvr\verilog.asm
.......\..........\....\....\_primary.dat
.......\..........\....\....\_primary.vhd
.......\..........\....\.s232\verilog.asm
.......\..........\....\.....\_primary.dat
.......\..........\....\.....\_primary.vhd
.......\..........\....\....._test_v\verilog.asm
.......\..........\....\............\_primary.dat
.......\..........\....\............\_primary.vhd
.......\..........\....\testbench\verilog.asm
.......\..........\....\.........\_primary.dat
    

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