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Title: trafficled Download
 Description: Digital circuit design of a traffic light with a main road and bypass roads are two different time control processing, using vhdl language compiler, with full report and code.
 Downloaders recently: [More information of uploader fghkfhu]
  • [Traffic] - Using ALTERA on DE2 platform, use the Ve
  • [trafficlight] - Design of traffic lights at the crossroa
File list (Check if you may need any files):
交通灯实现代码\chao.vcd
..............\chaolu.bld
..............\chaolu.cmd_log
..............\chaolu.ise
..............\chaolu.ise_ISE_Backup
..............\chaolu.lso
..............\chaolu.ngc
..............\chaolu.ngd
..............\chaolu.ngr
..............\chaolu.ntrc_log
..............\chaolu.prj
..............\chaolu.restore
..............\chaolu.stx
..............\chaolu.syr
..............\chaolu.ucf
..............\chaolu.vhd
..............\chaolu.xst
..............\chaolu_fpe.prj
..............\chaolu_ise10migration.zip
..............\chaolu_map.map
..............\chaolu_map.mrp
..............\chaolu_map.ngm
..............\chaolu_prev_built.ngd
..............\chaolu_summary.html
..............\chaolu_vhdl.prj
..............\.......xdb\tmp\ise\version
..............\..........\...\...\__OBJSTORE__\common\HierarchicalDesign\HDProject
..............\..........\...\...\............\......\..................\HDProject_StrTbl
..............\..........\...\...\............\......\__stored_object_table__
..............\..........\...\...\............\ExpandedNetlistEngine\Colors
..............\..........\...\...\............\.....................\Colors_StrTbl
..............\..........\...\...\............\.....................\Groups
..............\..........\...\...\............\.....................\Groups_StrTbl
..............\..........\...\...\............\HierarchicalDesign\HDProject\HDProject
..............\..........\...\...\............\..................\.........\HDProject_StrTbl
..............\..........\...\...\............\..................\__stored_object_table__
..............\..........\...\...\............\PnAutoRun\Scripts\RunOnce_tcl
..............\..........\...\...\............\.........\.......\RunOnce_tcl_StrTbl
..............\..........\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main
..............\..........\...\...\............\................\................\dpm_project_main_StrTbl
..............\..........\...\...\............\................\__stored_objects__
..............\..........\...\...\............\................\__stored_objects___StrTbl
..............\..........\...\...\............\................\__stored_object_table__
..............\..........\...\...\............\................Gui\GuiProjectData
..............\..........\...\...\............\...................\GuiProjectData_StrTbl
..............\..........\...\...\............\xreport\Gc_RvReportViewer-Current-Module
..............\..........\...\...\............\.......\Gc_RvReportViewer-Current-Module_StrTbl
..............\..........\...\...\............\.......\Gc_RvReportViewer-Module-Data-chaolu
..............\..........\...\...\............\.......\Gc_RvReportViewer-Module-Data-chaolu_StrTbl
..............\..........\...\...\............\.......\Gc_RvReportViewer-Module-Data-Factory-Default
..............\..........\...\...\............\.......\Gc_RvReportViewer-Module-Data-Factory-Default_StrTbl
..............\..........\...\...\............\.......\Gc_RvReportViewer-Module-Data-TOP
..............\..........\...\...\............\.......\Gc_RvReportViewer-Module-Data-TOP_StrTbl
..............\..........\...\...\..REGISTRY__\Autonym\regkeys
..............\..........\...\...\............\bitgen\regkeys
..............\..........\...\...\............\common\regkeys
..............\..........\...\...\............\.pldfit\regkeys
..............\..........\...\...\............\dumpngdio\regkeys
..............\..........\...\...\............\ExpandedNetlistEngine\regkeys
..............\..........\...\...\............\fuse\regkeys
..............\..........\...\...\............\HierarchicalDesign\HDProject\regkeys
..............\..........\...\...\............\..................\regkeys
..............\..........\...\...\............\hprep6\regkeys
..............\..........\...\...\............\idem\regkeys
..............\..........\...\...\............\map\regkeys
..............\..........\...\...\............\netgen\regkeys
..............\..........\...\...\............\.gc2edif\regkeys
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