Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: fir_sine Download
 Description: This implementation is moderately memory efficient because it stores only the first Pi/2 radians of sine values. The second Pi/2 radians is a mirror image of the first in time and the second Pi radians is a mirror image in amplitude of the first Pi radians. Memory could be saved if the increments were recorded rather than each absolute value. Fewer bits per value would be needed, however, extra hardware would be needed for an adder.
 Downloaders recently: [More information of uploader suriyan.vlsi]
 To Search: VHDL mirror
  • [I2C_Verilog] - I2C (Intel-Integrated Circuit bus) contr
  • [UART] - 4 byte real interfaces for UART transmis
File list (Check if you may need any files):
fir_sine\fir.m
........\fir.vhd
........\sine.vhd
fir_sine
........\FIR FILTERS.doc
    

CodeBus www.codebus.net