File list (Check if you may need any files):
16位CPU的verilog代码\cpu\CPU.v
....................\...\decoder.v
....................\...\ram.v
....................\...\RISC_CPU设计练习.doc
....................\...\rom.v
....................\...\test.v
....................\...\test1.dat
....................\...\test1.pro
....................\...\test2.dat
....................\...\test2.pro
....................\...\test3.dat
....................\...\test3.pro
....................\...\test4.dat
....................\...\test4.pro
....................\...\test5.dat
....................\...\test5.PRO
....................\...\transcript
....................\...\vsim.wlf
....................\...\模拟结果.txt
....................\...\说明.txt
....................\cpu.rar
....................\cpu
16位CPU的verilog代码
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