Description: Using Verilog language production of 17 Road PWM signal to control 17 Servos, can be used as IP core to the AVALON bus, in the nios IDE in control with the C language.
- [pwm] - PWM Verilog HDL code and the bottom of t
- [PWM] - VKDL languages with PWM control procedur
- [lai_PWM] - FPGA in Verilog source code under the PW
- [PWM_VerilogHDL] - altera company' s Web site the detail
- [audio_up8sample] - verilog code.upsample audio date 8 times
- [pwm] - Language implementation using vhdl wave
- [PWM] - PWM hardware using Verilog implementatio
- [pwm] - PWM IP core design,which period and duty
File list (Check if you may need any files):
pwm\driver\pwm.h
...\......\pwm_regs.h
...\......\pwm_regs.h~
...\pwm17.v
...\pwm17_hw.tcl
...\pwm17_hw.tcl~
...\driver
pwm
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