经典Verilog HDL语言例子48例\addac.v
...........................\addbook1.v
...........................\addbook2.v
...........................\addbook3.v
...........................\addbook4.v
...........................\clock.v
...........................\compinst.v
...........................\control.c
...........................\counter.v
...........................\counters_altera.v
...........................\div16.v
...........................\fifo.v
...........................\latchinf.v
...........................\mult16.v
...........................\multiplier_16x16.v
...........................\mult_piped_8x8_2sC.v
...........................\mux.v
...........................\ram256x8_altera.v
...........................\reg12.v
...........................\reginf.v
...........................\S95.log
...........................\SPI_interface.v
...........................\statmach_altera.v
...........................\tcounter.v
...........................\testing.v
...........................\traffic_ls.v
...........................\uart.v
...........................\wpulse.v
...........................\使用说明请参看右侧注释====〉〉.txt
...........................\Examples of Verilog\BNF.txt
...........................\...................\Compile Examples.v
...........................\...................\CompileFSM.v
...........................\...................\Examples of Verilog.v
...........................\...................\examplesA.txt
...........................\...................\examplesB.doc
...........................\...................\examplesB.txt
...........................\...................\FSM.cdr
...........................\...................\Seqdet.v
...........................\Examples of Verilog
经典Verilog HDL语言例子48例