Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: FIFO Download
 Description: Speeds up to 130MHz for high-speed data acquisition program source code for the Verilog
 Downloaders recently: [More information of uploader fl200600833]
 To Search:
  • [verilogFIR] - The source of the FIR digital filter for
File list (Check if you may need any files):
高速FIFO(Verilog设计)速度高达130Mhz\fifo\src\fifomem.v
...................................\....\...\rptr_empty.v
...................................\....\...\sync_r2w.v
...................................\....\...\sync_w2r.v
...................................\....\...\wptr_full.v
...................................\....\...\fifo1.v
...................................\....\...\test.v
...................................\....\sim.bat
...................................\....\.cript\prepare.do
...................................\....\......\sim.do
...................................\....\......\transcript
...................................\....\......\work\_info
...................................\....\......\....\fifomem\_primary.vhd
...................................\....\......\....\.......\verilog.asm
...................................\....\......\....\.......\_primary.dat
...................................\....\......\....\rptr_empty\_primary.vhd
...................................\....\......\....\..........\verilog.asm
...................................\....\......\....\..........\_primary.dat
...................................\....\......\....\sync_r2w\_primary.vhd
...................................\....\......\....\........\verilog.asm
...................................\....\......\....\........\_primary.dat
...................................\....\......\....\.....w2r\_primary.vhd
...................................\....\......\....\........\verilog.asm
...................................\....\......\....\........\_primary.dat
...................................\....\......\....\wptr_full\_primary.vhd
...................................\....\......\....\.........\verilog.asm
...................................\....\......\....\.........\_primary.dat
...................................\....\......\....\fifo1\_primary.vhd
...................................\....\......\....\.....\verilog.asm
...................................\....\......\....\.....\_primary.dat
...................................\....\......\....\test\_primary.vhd
...................................\....\......\....\....\verilog.asm
...................................\....\......\....\....\_primary.dat
...................................\....\......\run.f
...................................\....\......\t1
...................................\....\......\t2
...................................\....\......\t3
...................................\....\......\t4.rc
...................................\....\......\fifo.fsdb
...................................\....\nlint.bat
...................................\....\debussy\Debussy.exeLog\debussy.rc
...................................\....\.......\..............\turbo.log
...................................\....\.......\..............\Debussy.exe.cmd
...................................\....\.......\..............\compiler.log
...................................\....\.......\..............\ToNetlist.log
...................................\....\.......\..............\Debussy.exe.cmd.bak
...................................\....\.......\debussy.rc
...................................\....\nlint\nLint.exeLog\nLint.rc
...................................\....\.....\............\turbo.log
...................................\....\.....\............\compiler.log
...................................\....\.....\nLint.rc
...................................\....\.....\nLint.ds
...................................\....\.....\nlReport.rdb
...................................\使用说明请参看右侧注释====〉〉.txt
...................................\fifo\script\work\fifomem
...................................\....\......\....\rptr_empty
...................................\....\......\....\sync_r2w
...................................\....\......\....\sync_w2r
...................................\....\......\....\wptr_full
...................................\....\......\....\fifo1
...................................\....\......\....\test
...................................\....\......\work
...................................\....

CodeBus www.codebus.net