Description: Prepared using look-up table method of verilog DDS program, save the use of IP core implementation requires resources, software for the ISE,
- [dds(heli)] - DDS using verilog realized, can be squar
- [Kaifang] - Prepared using ISE verilog program to ac
- [SwitchLed] - FPGA entry procedures. Programming for b
File list (Check if you may need any files):
MyDDS\MyDDS.ise
.....\MyDDS.restore
.....\test_mydds.v
.....\test_mydds_v.udo
.....\test_mydds_v.fdo
.....\transcript
.....\work\_info
.....\....\sin0\_primary.vhd
.....\....\....\verilog.asm
.....\....\....\_primary.dat
.....\....\cos0\_primary.vhd
.....\....\....\verilog.asm
.....\....\....\_primary.dat
.....\....\mydds\_primary.vhd
.....\....\.....\verilog.asm
.....\....\.....\_primary.dat
.....\....\test_mydds_v\_primary.vhd
.....\....\............\verilog.asm
.....\....\............\_primary.dat
.....\....\glbl\_primary.vhd
.....\....\....\verilog.asm
.....\....\....\_primary.dat
.....\vsim.wlf
.....\MyDDS.ise_ISE_Backup
.....\mydds.v
.....\shuruyuan_summary.html
.....\mydds_summary.html
.....\sin0.v
.....\cos0.v
.....\work\sin0
.....\....\cos0
.....\....\mydds
.....\....\test_mydds_v
.....\....\glbl
.....\work
.....\_xmsgs
MyDDS
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