Description: Computer component experiments designed more CPU clock cycles, including VHDL code design, test circuit, test detailed screenshots.
- [8-cpu] - 8-bit CPU of the VHDL design, 16 instruc
- [mult] - err
- [CPU] - Ago in the school curriculum design, the
- [MICO8_DEMO_03_18_08.ZIP] - Lattice super-streamlined eight soft-cor
- [mux4] - 4 Multiplier VHDL language design, and s
- [5_lined_cpu] - Simple line 5 of the CPU logic design ve
- [cpu] - verilog prepared by a simple CPU, for re
- [ALU] - ALU
File list (Check if you may need any files):
多时钟周期CPU设计\报告文档.docx
.................\MulCyl_CPU071221093.rar
.................\visio图\多周期指令执行周期.vsd
.................\.......\状态图.vsd
.................\.......\多周期CPU设计.vsd
.................\截图\1.PNG
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.................\visio图
.................\截图
多时钟周期CPU设计
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