Description: The base 2 of the 16 points, each 16-point FFT calculation modelsim full engineering, simulation can be directly run
- [cf_fft_2048v] - FPGA-based 2048-point FFT verilog the so
- [FFT] - Verilog implementation FFT module for th
File list (Check if you may need any files):
fft_model\addr_gen.v
.........\addr_gen.v.bak
.........\Angle_Rom.v
.........\buttfly.v
.........\code.rar
.........\control.v
.........\control.v.bak
.........\fft_model.cr.mti
.........\fft_model.mpf
.........\inimag.txt
.........\inreal.txt
.........\MUX.v
.........\MUX.v.bak
.........\ram.v
.........\ram.v.bak
.........\ram_in.v
.........\ram_in.v.bak
.........\ram_out.v
.........\ram_out.v.bak
.........\tb.v
.........\tb.v.bak
.........\tb2.v
.........\top.v
.........\top.v.bak
.........\transcript
.........\wlft5g994d
.........\wlft6ye2q4
.........\wlft928bhg
.........\wlftdjxq6v
.........\wlftfyezx0
.........\wlftnkqb11
.........\wlftnr0dw5
.........\wlftrevfkf
.........\wlftvyk4q6
.........\wlftwhgrqf
.........\.ork\_info
.........\....\.opt\work_@angle_@rom_fast.asm
.........\....\....\work_@angle_@rom_fast.dt2
.........\....\....\work_@m@u@x_fast.asm
.........\....\....\work_@m@u@x_fast.dt2
.........\....\....\work_addr_gen_fast.asm
.........\....\....\work_addr_gen_fast.dt2
.........\....\....\work_buttfly_fast.asm
.........\....\....\work_buttfly_fast.dt2
.........\....\....\work_control_fast.asm
.........\....\....\work_control_fast.dt2
.........\....\....\work_ram_fast.asm
.........\....\....\work_ram_fast.dt2
.........\....\....\work_ram_in_fast.asm
.........\....\....\work_ram_in_fast.dt2
.........\....\....\work_ram_out_fast.asm
.........\....\....\work_ram_out_fast.dt2
.........\....\....\work_testbench_fast.asm
.........\....\....\work_testbench_fast.dt2
.........\....\....\work_top_fast.asm
.........\....\....\work_top_fast.dt2
.........\....\....\work__info
.........\....\....\_deps
.........\....\top\_primary.dat
.........\....\...\_primary.vhd
.........\....\.estbench\_primary.dat
.........\....\.........\_primary.vhd
.........\....\.b2\_primary.dat
.........\....\...\_primary.vhd
.........\....\ram_out\_primary.dat
.........\....\.......\_primary.vhd
.........\....\....in\_primary.dat
.........\....\......\_primary.vhd
.........\....\...\_primary.dat
.........\....\...\_primary.vhd
.........\....\control\_primary.dat
.........\....\.......\_primary.vhd
.........\....\buttfly\_primary.dat
.........\....\.......\_primary.vhd
.........\....\addr_gen\_primary.dat
.........\....\........\_primary.vhd
.........\....\@m@u@x\_primary.dat
.........\....\......\_primary.vhd
.........\....\.angle_@rom\_primary.dat
.........\....\...........\_primary.vhd
.........\....\_temp
.........\....\_opt
.........\....\top
.........\....\testbench
.........\....\tb2
.........\....\ram_out
.........\....\ram_in
.........\....\ram
.........\....\control
.........\....\buttfly
.........\....\addr_gen
.........\....\@m@u@x
.........\....\@angle_@rom
.........\work
fft_model
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