dmac\DMAC_ENG_intro.ppt
....\DMA结构1.ppt
....\hdl\dmac_ctl.v
....\...\dmac_ctl.v.bak
....\...\dmac_reg_if.v
....\...\dmac_reg_if.v.bak
....\...\dmac_top.v
....\...\dmac_top.v.bak
....\sim\file.f
....\...\file.f.bak
....\...\inca_libs\.ncv.lock
....\...\.........\cds.lib
....\...\.........\hdl.var
....\...\.........\snap.nc\.elab.args
....\...\.........\.......\.hard.args
....\...\.........\.......\.ncv.lock
....\...\.........\.......\ncverilog.args
....\...\.........\worklib\.cdsvmod
....\...\.........\.......\.inca.db.148.win32
....\...\.........\.......\cdsinfo.tag
....\...\.........\.......\inca.win32.148.pak
....\...\ncsim.shm\ncsim.dsn
....\...\.........\ncsim.trn
....\...\ncverilog.key
....\...\ncverilog.log
....\...\run.bat
....\...\rungui.bat
....\...\transcript
....\...\verilog.dsn
....\...\verilog.trn
....\...\verilog.vcd
....\tb\host_model.v.bak
....\..\host_model11.v
....\..\memory_model.txt.bak
....\..\memory_model.v
....\..\memory_model.v.bak
....\..\tb.v
....\..\tb.v.bak
....\..\timescale.v
....\XC_MAS_DMAC_V0.11.doc
....\sim\inca_libs\snap.nc
....\...\.........\worklib
....\...\inca_libs
....\...\ncsim.shm
....\hdl
....\sim
....\tb
dmac