Description: Written in VHDL language using a seven-segment digital tube display program, follow-up there is divider, data selector, counters procedures, software platform is Quartus II 7.2, the final adoption of these small modules can be combined to produce a clock or other arbitrary binary counter, suitable for beginners, through these procedures, new to VHDL learners can be a step by step to the awareness and understanding of VHDL, the last through the design of a practical function of the circuit, to increase the learner' s sense of achievement and interest in learning. All programs have successfully passed the hardware and software debugging, hardware platform is designed by a development of their own school board, it is necessary to know can contact me. Contact QQ: 782649157
To Search:
- [4x4dataselector.Rar] - 4x4 with the VHDL data selectors, under
- [VHDL] - VHDL digital clock digital electronic cl
- [dled] - VHDL language, dynamic digital tube disp
- [SELCT16_1] - 16 selected a data selector, by controll
- [seg7] - VHDL language based on seven-segment LED
File list (Check if you may need any files):
qq deled\db\deled.asm.qmsg
........\..\deled.cbx.xml
........\..\deled.cmp.bpm
........\..\deled.cmp.cdb
........\..\deled.cmp.ecobp
........\..\deled.cmp.hdb
........\..\deled.cmp.logdb
........\..\deled.cmp.rdb
........\..\deled.cmp.tdb
........\..\deled.cmp0.ddb
........\..\deled.cmp_bb.cdb
........\..\deled.cmp_bb.hdb
........\..\deled.cmp_bb.logdb
........\..\deled.cmp_bb.rcf
........\..\deled.dbp
........\..\deled.db_info
........\..\deled.eco.cdb
........\..\deled.fit.qmsg
........\..\deled.hier_info
........\..\deled.hif
........\..\deled.map.bpm
........\..\deled.map.cdb
........\..\deled.map.ecobp
........\..\deled.map.hdb
........\..\deled.map.logdb
........\..\deled.map.qmsg
........\..\deled.map_bb.cdb
........\..\deled.map_bb.hdb
........\..\deled.map_bb.logdb
........\..\deled.pre_map.cdb
........\..\deled.pre_map.hdb
........\..\deled.psp
........\..\deled.pss
........\..\deled.rtlv.hdb
........\..\deled.rtlv_sg.cdb
........\..\deled.rtlv_sg_swap.cdb
........\..\deled.sgdiff.cdb
........\..\deled.sgdiff.hdb
........\..\deled.signalprobe.cdb
........\..\deled.sim.cvwf
........\..\deled.sim.hdb
........\..\deled.sim.qmsg
........\..\deled.sim.rdb
........\..\deled.sld_design_entry.sci
........\..\deled.sld_design_entry_dsc.sci
........\..\deled.syn_hier_info
........\..\deled.tan.qmsg
........\..\deled.tis_db_list.ddb
........\..\prev_cmp_deled.qmsg
........\..\prev_cmp_deled.sim.qmsg
........\..\wed.wsf
........\deled.asm.rpt
........\deled.bsf
........\deled.done
........\deled.fit.rpt
........\deled.fit.smsg
........\deled.fit.summary
........\deled.flow.rpt
........\deled.map.rpt
........\deled.map.summary
........\deled.pin
........\deled.qpf
........\deled.qsf
........\deled.qws
........\deled.sim.rpt
........\deled.tan.rpt
........\deled.tan.summary
........\deled.vhd
........\deled.vwf
........\db
qq deled
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