Description: VHDL hardware language using BPSK modulation and demodulation system, the preparation, simulation adopted, the source code
- [VHDLGW48] - ASK Modulation and Demodulation Simulati
- [Code2] - SPCE061A Singlechip to as the core, thro
- [FSKPSK] - FSK and PSK modulation and demodulation
- [interleave] - Data interleaver verilog HDL source file
- [1B1] - VHDL-based programmable BPSk modulation
- [bpsk] - Based on the vhdl language bpsk programm
- [Cadence] - cadence of the English tutorials, from i
- [50846288C] - verilog hardware, programming bpsk Modul
- [ModulationandDemodulation] - Simulation signals and systems using lab
- [bpsk] - FPGA-Based Digital Modulator BPSK, for p
File list (Check if you may need any files):
cpsk\adder32b.bsf
....\adder32b.vhd
....\cnt.bsf
....\cnt.vhd
....\cnt1.bsf
....\cnt1.vhd
....\cpsk.asm.rpt
....\cpsk.bdf
....\cpsk.cdf
....\cpsk.done
....\cpsk.dpf
....\cpsk.fit.rpt
....\cpsk.fit.smsg
....\cpsk.fit.summary
....\cpsk.flow.rpt
....\cpsk.map.rpt
....\cpsk.map.summary
....\cpsk.pin
....\cpsk.pof
....\cpsk.qpf
....\cpsk.qsf
....\cpsk.qws
....\cpsk.sof
....\cpsk.tan.rpt
....\cpsk.tan.summary
....\cpsk_assignment_defaults.qdf
....\data_rom.bsf
....\data_rom.cmp
....\data_rom.vhd
....\data_rom1.bsf
....\data_rom1.cmp
....\data_rom1.vhd
....\.b\altsyncram_ps21.tdf
....\..\cpsk.db_info
....\..\cpsk.eco.cdb
....\..\cpsk.sld_design_entry.sci
....\mux21a.bsf
....\mux21a.vhd
....\not1.bsf
....\not1.vhd
....\prb.bsf
....\prb.vhd
....\reg32b.bsf
....\reg32b.inc
....\reg32b.vhd
....\sin.mif
....\db
cpsk
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