Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: miaobiao Download
 Description: VHDL language stopwatch and digital control on a total of negative dynamic display decimal values
 Downloaders recently: [More information of uploader 376369127]
 To Search:
  • [VerilogHDL] - Explain the very good Verilog HDL teachi
File list (Check if you may need any files):
miaobiao
........\clock.vhd
........\db
........\..\add_sub_cnh.tdf
........\..\add_sub_llh.tdf
........\..\miaobiao.db_info
........\..\miaobiao.eco.cdb
........\..\miaobiao.sld_design_entry.sci
........\..\prev_cmp_miaobiao.asm.qmsg
........\..\prev_cmp_miaobiao.fit.qmsg
........\..\prev_cmp_miaobiao.map.qmsg
........\..\prev_cmp_miaobiao.qmsg
........\..\prev_cmp_miaobiao.tan.qmsg
........\fp.bsf
........\fp.vhd
........\miaobiao.asm.rpt
........\miaobiao.bdf
........\miaobiao.cdf
........\miaobiao.done
........\miaobiao.dpf
........\miaobiao.fit.rpt
........\miaobiao.fit.summary
........\miaobiao.flow.rpt
........\miaobiao.gdf
........\miaobiao.map.rpt
........\miaobiao.map.summary
........\miaobiao.pin
........\miaobiao.pof
........\miaobiao.qpf
........\miaobiao.qsf
........\miaobiao.qws
........\miaobiao.sof
........\miaobiao.tan.rpt
........\miaobiao.tan.summary
........\miaobiao_assignment_defaults.qdf
........\xiaodou.bdf
........\xiaodou.bsf
........\xiaodou.vhd
    

CodeBus www.codebus.net