Description: According to the order provides ModelSim or Tcl/Tk language syntax, the simulation process simulation Cmd command followed by the preparation of the extension " do" macro file, and then direct the implementation of the DO file, you can complete the entire simulation process
File list (Check if you may need any files):
fpga_DO
.......\counter.do
.......\counter.v
.......\stimulus.do
.......\vsim.wlf
.......\work
.......\....\counter
.......\....\.......\verilog.asm
.......\....\.......\_primary.dat
.......\....\.......\_primary.vhd
.......\....\_info
.......\示例说明.doc
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