Description: Altera IP core of the integrity of the 8B10B encoder design process, including the Altera IP customization, simulation and realization of the whole process of
File list (Check if you may need any files):
Ateral IP
.........\Project
.........\.......\IP_ENC
.........\.......\Simulation
.........\.......\..........\220model.v
.........\.......\..........\altera_mf.v
.........\.......\..........\sgate.v
.........\.......\..........\sim.do
.........\.......\..........\wave.do
.........\Solution
.........\........\ENC.bsf
.........\........\ENC.v
.........\........\ENC_aot1151_enc8b10b.v
.........\........\IP_ENC
.........\........\......\ENC.bsf
.........\........\......\ENC.cmp
.........\........\......\ENC.html
.........\........\......\ENC.inc
.........\........\......\ENC.v
.........\........\......\ENC.vo
.........\........\......\ENC_aot1151_enc8b10b.ocp
.........\........\......\ENC_aot1151_enc8b10b.tcl
.........\........\......\ENC_aot1151_enc8b10b.v
.........\........\......\ENC_bb.v
.........\........\......\ENC_inst.v
.........\........\......\ENC_run_modelsim_verilog
.........\........\......\ENC_run_modelsim_vhdl
.........\........\......\ENC_simfiles.vnc
.........\........\......\ENC_tb.v
.........\........\......\hw
.........\........\......\..\build
.........\........\......\..\.....\b0iwe
.........\........\......\iptb_ed8b10b_temp41893
.........\........\......\......................\simgen
.........\........\Simulation
.........\........\..........\220model.v
.........\........\..........\altera_mf.v
.........\........\..........\ENC.vo
.........\........\..........\ENC_tb.v
.........\........\..........\sgate.v
.........\........\..........\sim.do
.........\........\..........\wave.do
.........\........\TOPIP.bdf
.........\........\TOPIP.qpf
.........\........\TOPIP.qsf
.........\示例说明.doc
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