2009 Intelligent all-digital phase-locked loop des - CodeBus

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Software Engineering

Title: 2009

Category:
Project Design
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[PDF]
File Size:
185kb
Update:
2012-11-26
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Uploaded by:
cc189900

Description: Intelligent all-digital phase-locked loop design, FPGA-based implementation.

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To Search:

[adpll] - All-digital phase-locked loop function a
[fq_div] - pll 64 multiplier PLL multiplier used to
[newDPLLdesign] - The use of VHDL language design of digit
[DPLL(VHDL)] - The use of VHDL language of digital phas
[FPGA444555443] - FPGA-based all-digital phase-locked loop
[phase_lock_vhdl] - To achieve phase-locked loop in the VHDL
[FPGAphaselockedloopdesign] - Introduce the application of VHDL techni
[uniPaaSRIADemo] - uniPaaS RIA Demo Version 1.8
[VHDLDPLL] - VHDL-based all-digital phase-locked loop

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智能全数字锁相环的设计.pdf

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