Description: The tutorial more detailed introduction to the VHDL language, its syntax, the use of programming techniques from shallow to deep, are introduced, and gives 90 VHDL source code, including test procedures, the functional test code. As the document is a pdg format, PDG Reader folder, given to the reader.
To Search:
- [flvplayer] - flvplayer,you can use it!
- [modelsim] - Modelsim information on the study of Chi
- [eth_send] - Tsinghua University sdr project, network
File list (Check if you may need any files):
VHDL
....\100个VHDL的源代码
....\.................\10_function
....\.................\...........\10_bit_to_int.vhd
....\.................\...........\README.TXT
....\.................\11_wiredor
....\.................\..........\11_wiredor.vhd
....\.................\..........\README.TXT
....\.................\12_convert
....\.................\..........\12_convert.vhd
....\.................\..........\README.TXT
....\.................\13_SHL
....\.................\......\13_SHL.VHD
....\.................\......\README.TXT
....\.................\14_MVL7_functions
....\.................\.................\14_MVL7_functions.vhd
....\.................\.................\README.TXT
....\.................\15_MUX41
....\.................\........\15_MUX41.VHD
....\.................\........\15_MVL7_functions.vhd
....\.................\........\15_MVL7_syn_types.vhd
....\.................\........\15_test_vectors_mux41.vhd
....\.................\........\15_TYPES.VHD
....\.................\........\README.TXT
....\.................\16_MUX
....\.................\......\16_multiple_mux.vhd
....\.................\......\16_MVL7_functions.vhd
....\.................\......\16_test_vectors.vhd
....\.................\......\16_TYPES.VHD
....\.................\......\README.TXT
....\.................\......\TYPES.VHD
....\.................\17_parity
....\.................\.........\17_parity.vhd
....\.................\.........\17_test_bench.vhd
....\.................\.........\README.TXT
....\.................\18_LIB
....\.................\......\18_tech_lib.vhd
....\.................\......\18_test_lib.vhd
....\.................\......\README.TXT
....\.................\19_test_194
....\.................\...........\19_test_194.vhd
....\.................\1_ADDER
....\.................\.......\1_ADDER
....\.................\.......\.......\1_ADDER.exp
....\.................\.......\.......\files
....\.................\.......\.......\.....\L1.rpt
....\.................\.......\.......\.....\L2.rpt
....\.................\.......\.......\.....\L3.rpt
....\.................\.......\.......\workdirs
....\.................\.......\.......\........\aa
....\.................\.......\.......\........\..\ADDER.sim
....\.................\.......\.......\........\..\ADDER.syn
....\.................\.......\.......\........\..\Anal.info
....\.................\.......\.......\........\..\Anal.out
....\.................\.......\.......\........\WORK
....\.................\.......\.......\........\....\Anal.info
....\.................\.......\.......\........\....\Anal.out
....\.................\.......\.......\........\....\BIT_RTL_ADDER.sim
....\.................\.......\.......\........\....\BIT_RTL_ADDER.syn
....\.................\.......\1_adder.acf
....\.................\.......\1_adder.hif
....\.................\.......\1_adder.mmf
....\.................\.......\1_ADDER.VHD
....\.................\.......\bir_rtl_adder.acf
....\.................\.......\bir_rtl_adder.hif
....\.................\.......\bir_rtl_adder.mmf
....\.................\.......\bir_rtl_adder.tdf
....\.................\.......\bit_rtl_adder.acf
....\.................\.......\bit_rtl_adder.hif
....\.................\.......\bit_rtl_adder.mmf
....\.................\.......\bit_rtl_adder.vhd
....\.................\.......\LIB.DLS
....\.................\.......\README.TXT
....\.................\.......\U2268397.DLS
....\.................\20_test_159
....\.................\...........\20_test_159.vhd
....\.................\21_test_13a
....\.................\...........\21_test_13a.vhd
....\.................\22_deadlock
....\.................\...........\22_deadlock.vhd
....\.................\23_test_120
....\.................\...........\23_Test_120.vhd
....\.................\24_test_195
....\.................\...........\24_test_195.vhd
....\.................\25_test_1
....\.................\.........\25_test_1.vhd
....\.................\.........\25_test_1a.vhd
....\.................\26_test_74s
....\.................\...........\26_test_74s.vhd
....\.................\27_test_1
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