Description: As the CameraLink interface is currently based on a variety of cameras can not directly display, this article based on Xilinx' s Spartan 3 series FPGAXC3S1000-6FG456I designed a set of real-time display system, the system can be achieved without machine case through the system to complete the CameraLink cameras signal reception, cache, read and display systems use two SDRAM frame buffer as the input signals into the CameraLink frame rate of 75Hz, a resolution of 1 024 × 768 for XGA format signal, and using ADV7123JST chip digital-analog conversion, the chip output signal to the VGA port, through the VGA display monitor
- [cameralink] - Camera interface technology is now inclu
- [sram_controller] - Foreign sites found above sram_controlle
- [FPGAvhdl] - FPGA embedded applications a typical exa
- [URAT_VHDL] - URAT VHDL procedures and simulation, inc
- [fpga-dm9000a] - A project engineering, hardware contains
- [c_xapp260] - The use of Xilinx FPGA and Memory Interf
- [c_xapp454] - This the xilinx application note xapp454
- [verilog] - A good verilog of PPT on Chapter 1 of ED
- [DVI_Demo_C3H_PortB] - DVI_Demo_C3H_portB HSMC-DVI card
- [cmd] - DSP CMD file the linker command file, CM
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基于ＣａｍｅｒａＬｉｎｋ的实时显示技术研究.doc
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