UART_LCD_DAC Using RS232, FPGA and single-chip com

Title: UART_LCD_DAC

Category:
VHDL-FPGA-Verilog
Tags:
[C/C++] [源码]
File Size:
904kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
471778110

Description: Using RS232, FPGA and single-chip communications, the control FPGA and the LCD into da generate analog signals. FPGA part

Downloaders recently: [More information of uploader 471778110]

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[shiboqi(chugao)] - This program is embedded in the FPGA mic
[XC4VLX60MB_Lab3_RS232_ISE91] - FPGA design, In addition to logic design

File list (Check if you may need any files):

UART_LCD_DAC
............\DAC.v
............\device_usage_statistics.html
............\MAIN.v
............\MAIN_summary.html
............\mian.bgn
............\mian.bit
............\MIAN.bld
............\MIAN.cmd_log
............\mian.drc
............\MIAN.lfp
............\MIAN.lso
............\MIAN.ncd
............\MIAN.ngc
............\MIAN.ngd
............\MIAN.ngr
............\MIAN.pad
............\MIAN.par
............\MIAN.pcf
............\MIAN.prj
............\MIAN.stx
............\MIAN.syr
............\mian.twr
............\mian.twx
............\MIAN.unroutes
............\MIAN.ut
............\MIAN.xpi
............\MIAN.xst
............\MIAN_guide.ncd
............\MIAN_map.map
............\MIAN_map.mrp
............\MIAN_map.ncd
............\MIAN_map.ngm
............\MIAN_pad.csv
............\MIAN_pad.txt
............\MIAN_prev_built.ngd
............\MIAN_summary.html
............\MIAN_summary.xml
............\MIAN_usage.xml
............\RD.v
............\tdfun.v
............\TIME_WR_LCD.v
............\transcript
............\UART_LCD_DAC.ise
............\UART_LCD_DAC.ise_ISE_Backup
............\UART_LCD_DAC.ntrc_log
............\UART_LCD_DAC.restore
............\UART_WITH_FPGA_DPJ
............\..................\main
............\..................\main.c
............\..................\main.hex
............\..................\main.lnp
............\..................\main.LST
............\..................\main.M51
............\..................\main.OBJ
............\..................\main.Opt
............\..................\main.plg
............\..................\main.Uv2
............\..................\STARTUP.A51
............\..................\STARTUP.LST
............\..................\STARTUP.OBJ
............\UCF_FOR_DESIGN.cel
............\UCF_FOR_DESIGN.lfp
............\UCF_FOR_DESIGN.ucf
............\xst
............\...\dump.xst
............\...\........\MIAN.prj
............\...\........\........\ngx
............\...\........\........\...\notopt
............\...\........\........\...\opt
............\...\........\........\ntrc.scr
............\...\projnav.tmp
............\...\work
............\...\....\hdllib.ref
............\...\....\vlg2C
............\...\....\.....\_d_a_c.bin
............\...\....\vlg35
............\...\....\.....\tdfun.bin
............\...\....\vlg3D
............\...\....\.....\_t_i_m_e___w_r___l_c_d.bin
............\...\....\vlg4D
............\...\....\.....\_m_i_a_n.bin
............\...\....\vlg5E
............\...\....\.....\_r_d.bin
............\_impact.cmd
............\_impact.log
............\_ngo
............\....\netlist.lst
............\_pace.ucf
............\_xmsgs
............\......\bitgen.xmsgs
............\......\map.xmsgs
............\......\ngdbuild.xmsgs
............\......\par.xmsgs
............\......\trce.xmsgs
............\......\xst.xmsgs

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