Description: Verilog prepared with simple arithmetic unit (ALU), can be add, subtract, and, or, exclusive-OR, non-, left, and other functions shifted to right
- [fen] - Verilog, 4,5 dividers, five dividers rat
- [ALU] - ALU can be 16 kinds of operations (inclu
- [alu] - Prepared by using assembly language comp
- [control_fsm_rtl.vhd] - ALU FSMALU FSMALU FSMALU FSMALU FSMALU F
- [16weiyunsuanqi] - 16-bit computing design and the realizat
- [alu] - This is a 32-bit alu code, use verilog t
- [alu] - ALU modeling verilog codes and testbench
File list (Check if you may need any files):
alu
...\alu.cmd_log
...\alu.ise
...\alu.ise_ISE_Backup
...\alu.lso
...\alu.ngc
...\alu.ngr
...\alu.ntrc_log
...\alu.prj
...\alu.restore
...\alu.stx
...\alu.syr
...\alu.xst
...\alu_summary.html
...\xst
...\...\dump.xst
...\...\........\alu.prj
...\...\........\.......\ngx
...\...\........\.......\...\notopt
...\...\........\.......\...\opt
...\...\........\.......\ntrc.scr
...\...\projnav.tmp
...\...\work
...\...\....\hdllib.ref
...\...\....\vlg0A
...\...\....\.....\alu.bin
...\_xmsgs
...\......\xst.xmsgs
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