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Title: fr_div Download
 Description: DDS divider clock AHDL
 Downloaders recently: [More information of uploader sashaku21]
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  • [clk4] - clk4 clock divider is designed for FPGA
File list (Check if you may need any files):
fr_div
......\cmp_state.ini
......\db
......\..\fr_div-sim.vwf
......\..\fr_div.csf.msg
......\..\fr_div.db_info
......\..\fr_div.fr_div.csf.hdb
......\..\fr_div.fr_div.csf.rdb
......\..\fr_div.fr_div.db_entries.csf.cdb
......\..\fr_div.fr_div.sgate_entries.csf.cdb
......\..\fr_div.fr_div.sgate_entries.csf.hdb
......\..\fr_div.fr_div.ssf.hdb
......\..\fr_div.fr_div.ssf.rdb
......\..\fr_div.fr_div.tdb_netlist.csf.tdb
......\..\fr_div.fr_div.tim_manager.csf.ddb
......\..\fr_div.hif
......\..\fr_div.psf.hdb
......\..\fr_div.ssf.msg
......\..\fr_div_hier_info
......\..\fr_div_syn_hier_info
......\debug.fsf
......\fr_div.csf
......\fr_div.csf.rpt
......\fr_div.eqn
......\fr_div.pin
......\fr_div.pof
......\fr_div.psf
......\fr_div.quartus
......\fr_div.qws
......\fr_div.sof
......\fr_div.ssf
......\fr_div.ssf.rpt
......\fr_div.tdf
......\fr_div.vwf
......\release.fsf
    

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