Description: VHDL language is designed to be simple to use the CPU, the focus of the design of micro-operation code, and then design the components of CPU module designed the final design of the micro-operation microinstruction to verify the correctness of the design. Can achieve the basic add, subtract, multiply, divide, transfer, recycling and other operations.
- [cpu] - Realize the basic functions of the CPU,
- [16cpu] - To achieve 16-bit design of the contents
- [jamcpu] - jam CPU Simulator Design and Implementat
- [cpu] - Simple self-cpu, the development of the
- [poc] - VHDL language used on the output control
- [risc] - quartus II verilog
- [The_design_of_MIPS_CPU(VHDL)] - a complete document of MIPS CPU design ,
- [2410S_instructor] - 1. Embedded LINUX development of basic k
- [CPU] - The purpose of this project is to design
File list (Check if you may need any files):
cpu
...\alu.bsf
...\alu.vhd
...\br.bsf
...\br.vhd
...\control_unit.bsf
...\control_unit.vhd
...\cpu.asm.rpt
...\cpu.bdf
...\cpu.done
...\cpu.fit.rpt
...\cpu.fit.smsg
...\cpu.fit.summary
...\cpu.flow.rpt
...\cpu.map.rpt
...\cpu.map.summary
...\cpu.pin
...\cpu.qpf
...\cpu.qsf
...\cpu.qws
...\cpu.sim.rpt
...\cpu.tan.rpt
...\cpu.tan.summary
...\cpu.vwf
...\db
...\..\altsyncram_3ac1.tdf
...\..\altsyncram_js61.tdf
...\..\cpu.analyze_file.qmsg
...\..\cpu.asm.qmsg
...\..\cpu.cbx.xml
...\..\cpu.cmp.bpm
...\..\cpu.cmp.cdb
...\..\cpu.cmp.ecobp
...\..\cpu.cmp.hdb
...\..\cpu.cmp.logdb
...\..\cpu.cmp.rdb
...\..\cpu.cmp.tdb
...\..\cpu.cmp0.ddb
...\..\cpu.cmp_bb.cdb
...\..\cpu.cmp_bb.hdb
...\..\cpu.cmp_bb.logdb
...\..\cpu.cmp_bb.rcf
...\..\cpu.dbp
...\..\cpu.db_info
...\..\cpu.eco.cdb
...\..\cpu.eds_overflow
...\..\cpu.fit.qmsg
...\..\cpu.fnsim.cdb
...\..\cpu.fnsim.hdb
...\..\cpu.fnsim.qmsg
...\..\cpu.hier_info
...\..\cpu.hif
...\..\cpu.map.bpm
...\..\cpu.map.cdb
...\..\cpu.map.ecobp
...\..\cpu.map.hdb
...\..\cpu.map.logdb
...\..\cpu.map.qmsg
...\..\cpu.map_bb.cdb
...\..\cpu.map_bb.hdb
...\..\cpu.map_bb.logdb
...\..\cpu.pre_map.cdb
...\..\cpu.pre_map.hdb
...\..\cpu.psp
...\..\cpu.pss
...\..\cpu.rtlv.hdb
...\..\cpu.rtlv_sg.cdb
...\..\cpu.rtlv_sg_swap.cdb
...\..\cpu.sgdiff.cdb
...\..\cpu.sgdiff.hdb
...\..\cpu.signalprobe.cdb
...\..\cpu.sim.cvwf
...\..\cpu.sim.hdb
...\..\cpu.sim.qmsg
...\..\cpu.sim.rdb
...\..\cpu.simfam
...\..\cpu.sld_design_entry.sci
...\..\cpu.sld_design_entry_dsc.sci
...\..\cpu.syn_hier_info
...\..\cpu.tan.qmsg
...\..\cpu.tis_db_list.ddb
...\..\mux_frc.tdf
...\..\prev_cmp_cpu.asm.qmsg
...\..\prev_cmp_cpu.fit.qmsg
...\..\prev_cmp_cpu.map.qmsg
...\..\prev_cmp_cpu.qmsg
...\..\prev_cmp_cpu.sim.qmsg
...\..\prev_cmp_cpu.tan.qmsg
...\..\wed.wsf
...\ir.bsf
...\ir.vhd
...\lpm_ram_dq0.bsf
...\lpm_ram_dq0.cmp
...\lpm_ram_dq0.vhd
...\lpm_ram_dq0_waveforms.html
...\lpm_rom0.bsf
...\lpm_rom0.cmp
...\lpm_rom0.vhd
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