32bit_RISC_CPU
..............\32位RISC处理器软核的设计与验证.doc
..............\alu_test.v
..............\cpu.v
..............\cpu_1.0.pdf
..............\cpu_verilog
..............\...........\alu.v
..............\...........\cntrl_rf.v
..............\...........\cpu.v
..............\...........\dcache_top.v
..............\...........\decode.v
..............\...........\forward.v
..............\...........\interrupt.v
..............\...........\mpu.v
..............\...........\pc_gen.v
..............\...........\regfile.v
..............\...........\reg_ex.v
..............\...........\reg_id.v
..............\...........\reg_if.v
..............\...........\reg_mem.v
..............\...........\write_back.v
..............\POTATO_TEST
..............\...........\cpu_summary.html
..............\...........\cpu_verilog
..............\...........\...........\alu.v
..............\...........\...........\cntrl_rf.v
..............\...........\...........\cpu.v
..............\...........\...........\dcache_top.v
..............\...........\...........\decode.v
..............\...........\...........\forward.v
..............\...........\...........\interrupt.v
..............\...........\...........\mpu.v
..............\...........\...........\pc_gen.v
..............\...........\...........\regfile.v
..............\...........\...........\reg_ex.v
..............\...........\...........\reg_id.v
..............\...........\...........\reg_if.v
..............\...........\...........\reg_mem.v
..............\...........\...........\write_back.v
..............\...........\dcache_top_summary.html
..............\...........\isim
..............\...........\....\work
..............\...........\....\....\addr__decoder
..............\...........\....\....\.............\addr__decoder.h
..............\...........\....\....\.............\mingw
..............\...........\....\....\.............\.....\addr__decoder.obj
..............\...........\....\....\alu
..............\...........\....\....\...\alu.h
..............\...........\....\....\...\mingw
..............\...........\....\....\...\.....\alu.obj
..............\...........\....\....\cntrl__rf
..............\...........\....\....\.........\cntrl__rf.h
..............\...........\....\....\.........\mingw
..............\...........\....\....\.........\.....\cntrl__rf.obj
..............\...........\....\....\cpu
..............\...........\....\....\...\cpu.h
..............\...........\....\....\...\mingw
..............\...........\....\....\...\.....\cpu.obj
..............\...........\....\....\dcache
..............\...........\....\....\......\dcache.h
..............\...........\....\....\......\mingw
..............\...........\....\....\......\.....\dcache.obj
..............\...........\....\....\dcache__top
..............\...........\....\....\...........\dcache__top.h
..............\...........\....\....\...........\mingw
..............\...........\....\....\...........\.....\dcache__top.obj
..............\...........\....\....\decode
..............\...........\....\....\......\decode.h
..............\...........\....\....\......\mingw
..............\...........\....\....\......\.....\decode.obj
..............\...........\....\....\dram
..............\...........\....\....\....\dram.h
..............\...........\....\....\....\mingw
..............\...........\....\....\....\.....\dram.obj
..............\...........\....\....\flash__wbbus
..............\...........\....\....\............\flash__wbbus.h
..............\...........\....\....\............\mingw
..............\...........\....\....\............\.....\flash__wbbus.obj
..............\...........\....\....\forward
..............\...........\....\....\.......\forward.h
..............\...........\....\....\.......\mingw
..............\...........\....\....\.......\.....\forward.obj
..............\...........\....\....\glbl
..............\...........\....\....\....\glbl.h
..............\...........\....\....\....\mingw
..............\...........\....\....\....\.....\glbl.obj
..............\...........\....\....\hdllib.ref
..............\...