Description: VHDL language, full-featured serial modules (including DTR, RTS pin, etc.), in the CPLD device test
- [FPGA+DSS+UART] - Using FPGA to achieve arbitrary waveform
- [cyclic] - FPGA serial communication program, accep
- [UART] - Input clock 20M, the baud rate for 9600,
- [uart] - This is the UART controller, has been ru
- [Uart] - Using FPGA, VHDL realize the UART core,
- [transfer_1] - EDA experiment -UART serial port experim
- [uart_exam] - Written in VHDL serial, very good, and t
- [PROJECTS_IEEE] - list of a good number of ieee vlsi proje
- [auk_sdsdi] - for FPGA design ,written by Verilog HDL
- [VHDLFIFO] - NO
File list (Check if you may need any files):
uart
....\db
....\..\urat.asm.qmsg
....\..\urat.cbx.xml
....\..\urat.cmp.cdb
....\..\urat.cmp.hdb
....\..\urat.cmp.kpt
....\..\urat.cmp.logdb
....\..\urat.cmp.rdb
....\..\urat.cmp.tdb
....\..\urat.cmp0.ddb
....\..\urat.dbp
....\..\urat.db_info
....\..\urat.eco.cdb
....\..\urat.eds_overflow
....\..\urat.fit.qmsg
....\..\urat.hier_info
....\..\urat.hif
....\..\urat.map.cdb
....\..\urat.map.hdb
....\..\urat.map.logdb
....\..\urat.map.qmsg
....\..\urat.pre_map.cdb
....\..\urat.pre_map.hdb
....\..\urat.psp
....\..\urat.rtlv.hdb
....\..\urat.rtlv_sg.cdb
....\..\urat.rtlv_sg_swap.cdb
....\..\urat.sgdiff.cdb
....\..\urat.sgdiff.hdb
....\..\urat.signalprobe.cdb
....\..\urat.sim.hdb
....\..\urat.sim.qmsg
....\..\urat.sim.rdb
....\..\urat.sim_ori.vwf
....\..\urat.sld_design_entry.sci
....\..\urat.sld_design_entry_dsc.sci
....\..\urat.syn_hier_info
....\..\urat.tan.qmsg
....\..\wed.zsf
....\urat.asm.rpt
....\urat.cdf
....\urat.done
....\urat.dpf
....\urat.fit.rpt
....\urat.fit.smsg
....\urat.fit.summary
....\urat.flow.rpt
....\urat.map.rpt
....\urat.map.summary
....\urat.pin
....\urat.pof
....\urat.qpf
....\urat.qsf
....\urat.qws
....\urat.sim.rpt
....\urat.sof
....\urat.tan.rpt
....\urat.tan.summary
....\urat.vhd
....\urat.vwf
....\urat_description.txt
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