并入串出寄存器
..............\db
..............\..\vhdl5.asm.qmsg
..............\..\vhdl5.cbx.xml
..............\..\vhdl5.cmp.cdb
..............\..\vhdl5.cmp.hdb
..............\..\vhdl5.cmp.kpt
..............\..\vhdl5.cmp.logdb
..............\..\vhdl5.cmp.rdb
..............\..\vhdl5.cmp.tdb
..............\..\vhdl5.cmp0.ddb
..............\..\vhdl5.dbp
..............\..\vhdl5.db_info
..............\..\vhdl5.eco.cdb
..............\..\vhdl5.eds_overflow
..............\..\vhdl5.fit.qmsg
..............\..\vhdl5.hier_info
..............\..\vhdl5.hif
..............\..\vhdl5.map.cdb
..............\..\vhdl5.map.hdb
..............\..\vhdl5.map.logdb
..............\..\vhdl5.map.qmsg
..............\..\vhdl5.pre_map.cdb
..............\..\vhdl5.pre_map.hdb
..............\..\vhdl5.psp
..............\..\vhdl5.rtlv.hdb
..............\..\vhdl5.rtlv_sg.cdb
..............\..\vhdl5.rtlv_sg_swap.cdb
..............\..\vhdl5.sgdiff.cdb
..............\..\vhdl5.sgdiff.hdb
..............\..\vhdl5.signalprobe.cdb
..............\..\vhdl5.sim.hdb
..............\..\vhdl5.sim.qmsg
..............\..\vhdl5.sim.rdb
..............\..\vhdl5.sim.vwf
..............\..\vhdl5.sld_design_entry.sci
..............\..\vhdl5.sld_design_entry_dsc.sci
..............\..\vhdl5.syn_hier_info
..............\..\vhdl5.tan.qmsg
..............\..\wed.zsf
..............\vhdl5.asm.rpt
..............\vhdl5.done
..............\vhdl5.fit.rpt
..............\vhdl5.fit.smsg
..............\vhdl5.fit.summary
..............\vhdl5.flow.rpt
..............\vhdl5.map.rpt
..............\vhdl5.map.summary
..............\vhdl5.pin
..............\vhdl5.qpf
..............\vhdl5.qsf
..............\vhdl5.qws
..............\vhdl5.sim.rpt
..............\vhdl5.tan.rpt
..............\vhdl5.tan.summary
..............\Vhdl5.vhd
..............\vhdl5.vwf