fifo1 Asynchronous FIFO design includes testbench

Title: fifo1

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Category:
VHDL-FPGA-Verilog
Tags:
[ASM] [源码]
File Size:
32kb
Update:
2012-11-26
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Uploaded by:
heyong363033384

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File list (Check if you may need any files):

fifo1
.....\fifo1.cr.mti
.....\fifo1.mpf
.....\fifo1.v
.....\fifo1.v.bak
.....\fifo1_test.v
.....\fifo1_test.v.bak
.....\vsim.wlf
.....\work
.....\....\@gray@counter_2
.....\....\...............\verilog.asm
.....\....\...............\_primary.dat
.....\....\...............\_primary.vhd
.....\....\fifo1
.....\....\.....\verilog.asm
.....\....\.....\_primary.dat
.....\....\.....\_primary.vhd
.....\....\fifo1_test
.....\....\..........\verilog.asm
.....\....\..........\_primary.dat
.....\....\..........\_primary.vhd
.....\....\_info

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