Description: Easy process to produce Sqrt, sine, and cosine tables, easy to read
- [sine] - VerilogHDL have achieved with Sine Wavef
- [sine_testbench] - Sine generator in VHDL.
File list (Check if you may need any files):
GenerateTable
.............\debug
.............\.....\GenerateTable.exe
.............\.....\GenerateTable.ilk
.............\.....\GenerateTable.pdb
.............\.....\Sqrt.table
.............\.....\Trig_COS.table
.............\.....\Trig_SIN.table
.............\GenerateTable
.............\.............\Debug
.............\.............\.....\BuildLog.htm
.............\.............\.....\GenerateTable.exe.embed.manifest
.............\.............\.....\GenerateTable.exe.embed.manifest.res
.............\.............\.....\GenerateTable.exe.intermediate.manifest
.............\.............\.....\GenerateTable.obj
.............\.............\.....\GenerateTable.pch
.............\.............\.....\mt.dep
.............\.............\.....\stdafx.obj
.............\.............\.....\vc80.idb
.............\.............\.....\vc80.pdb
.............\.............\GenerateTable.cpp
.............\.............\GenerateTable.vcproj
.............\.............\GenerateTable.vcproj.F9A91B9AC936479.Administrator.user
.............\.............\GenerateTable.vcproj.Pathfinders.Administrator.user
.............\.............\ReadMe.txt
.............\.............\Sqrt.table
.............\.............\stdafx.cpp
.............\.............\stdafx.h
.............\.............\Trig_COS.table
.............\.............\Trig_SIN.table
.............\GenerateTable.ncb
.............\GenerateTable.sln
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