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8 Queen
Date : 2008-10-13 Size : 805byte User : hzw

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StateCAD design with a
Date : 2008-10-13 Size : 13.07kb User : 程凯

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Cycle of double-ended queue, as well as the establishment of some simple operations such as insert, delete.
Date : 2008-10-13 Size : 1.05kb User : 周任红

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jsp+ access the development of mobile phones online sales site 1. to enter the
Date : 2008-10-13 Size : 718.89kb User : shi

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Keil prepared in which can run on the 80C51 single-chip calculator program. Can realize simple addition and subtraction, multiplication and division calculations.
Date : 2008-10-13 Size : 12.79kb User : Lee

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ISE tools used in the design
Date : 2008-10-13 Size : 341.28kb User : 程凯

Quantum evolutionary algorithm performance directly affected by the quantum spin the revolving door method of calculating the impact angle. This paper presents an improved quantum evolutionary algorithm, the core is desi
Date : 2008-10-13 Size : 362.84kb User : xq

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Modular Design of a simple design, source code, respectively, with Verilog and VHDL description of the two languages, the design of top-level module from the 3 sub-module.
Date : 2008-10-13 Size : 406.52kb User : 程凯

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In Keil prepared to run in the Marquee 80C51 MCU test procedure can be used to test board.
Date : 2008-10-13 Size : 10.71kb User : Lee

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Parentheses matching algorithm is to determine ([(left bracket whether these three have the corresponding right parenthesis to match.
Date : 2008-10-13 Size : 798byte User : 周任红

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LVDS design for example to study the timing analysis ISE as well as the use of low-level device layout method in the bottom of the layout of LVDS device pin to bound methods, the bottom of the layout design flow, the und
Date : 2008-10-13 Size : 126.59kb User : 程凯

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Keil developed, you can run in the C51 series of single-chip clock procedures.
Date : 2008-10-13 Size : 24.24kb User : Lee
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