Other resource List Page 2871

Other resource list

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8b10b_encdec Downloaded：0: Written in VHDL coding 8B10B decoder realize, in the Xilinx platform validated.
Date : 2008-10-13 Size : 69.36kb User : 张开文
traffic Downloaded：0: Verilog realize the use of traffic lights to control Quartus II simulation platform
Date : 2008-10-13 Size : 141.95kb User : 许东滨
3des_vhdl Downloaded：0: 3 re-DES (3DES) encryption algorithm and the Q
Date : 2008-10-13 Size : 136.9kb User : 张开文
PID Downloaded：0: Realize the PID control Simulation shows
Date : 2008-10-13 Size : 35.31kb User : 梁利诚
BasicRSA Downloaded：0: RSA encryption algorithm of VHDL realize, through actual FPGA verification.
Date : 2008-10-13 Size : 9.28kb User : 张开文
mapxzhongyao Downloaded：0: The development of good instructions on MapX novice has a lot of help, practical, high
Date : 2008-10-13 Size : 15.05kb User : awen
MAJORITY_VOTER Downloaded：0: Verylog prepared Quartus II platform attached to a simple design example simulation waveforms
Date : 2008-10-13 Size : 73.63kb User : 许东滨
LEDWALK Downloaded：0: Verylog prepared Quartus II platform attached to a simple design example simulation waveforms
Date : 2008-10-13 Size : 84.17kb User : 许东滨
LEDWATER Downloaded：0: Water lights Verylog prepared Quartus II platform attached to a simple design example simulation waveforms
Date : 2008-10-13 Size : 91.94kb User : 许东滨
PLL Downloaded：0: PLL clock module Quartus II platform attached to a simple design example simulation waveforms
Date : 2008-10-13 Size : 788.28kb User : 许东滨
dianji Downloaded：0: Very good article on the motor control, in the campus downloaded for reference and learning
Date : 2008-10-13 Size : 951.13kb User : 付惠珍
cnt4 Downloaded：0: Counter Counter 4 is used by digital systems more basic logic devices. It not only records the number of input clock pulse, but also realize frequency, timing, producing beats, such as pulse and pulse sequence. For examp
Date : 2008-10-13 Size : 20.67kb User : sy

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