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DDR (double data rate) SDRAM controller reference design for Xilinx
Date : 2008-10-13 Size : 128.25kb User : 陈旭

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through different diode light, washing machines, said the different states. Who is changed, and turned around, washing, drying. Press P3_3, would cease.
Date : 2008-10-13 Size : 23.66kb User : SKY

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drive using serial digital display shows each from 0 to F, to eliminate cycle, a request updated seconds.
Date : 2008-10-13 Size : 10.6kb User : SKY

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direct frequency synthesis, pioneered provide some source document is dedicated ESP
Date : 2008-10-13 Size : 66.85kb User : 陈旭

I2C Bus Controller ALTERA the VHDL source code
Date : 2008-10-13 Size : 1.56mb User : 陈旭

PCI bus arbitration reference design, pioneered the Verilog code
Date : 2008-10-13 Size : 3.4kb User : 陈旭

PLD 8051 interface with the Xilinx Reference Design for the Verilog source code
Date : 2008-10-13 Size : 58.88kb User : 陈旭

ZBT SRAM controller reference design for Xilinx (ZBT SRAM, a high-speed synchronous SRAM)
Date : 2008-10-13 Size : 35.62kb User : 陈旭

ZBT SRAM controller reference design for Xilinx VHDL source code
Date : 2008-10-13 Size : 9kb User : 陈旭

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Freescale MCU then HC08GP32 LCD source
Date : 2008-10-13 Size : 15.2kb User : neo

standard SDR SDRAM controller reference design, the Lattice Verilog source code
Date : 2008-10-13 Size : 199.51kb User : 陈旭

Manchester codec Xilinx provide VHDL source code
Date : 2008-10-13 Size : 10.36kb User : 陈旭
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