Designed using VHDL language Cymometer, after verification, there is no problem

freqtest
........\cmp_state.ini
........\conver.vhd
........\counter32b.vhd
........\db
........\..\cntr_b08.tdf
........\..\cntr_ed8.tdf
........\..\cntr_pd8.tdf
........\..\freqtest.asm.qmsg
........\..\freqtest.cmp.cdb
........\..\freqtest.cmp.ddb
........\..\freqtest.cmp.hdb
........\..\freqtest.cmp.rdb
........\..\freqtest.cmp.tdb
........\..\freqtest.dat_manager.dat
........\..\freqtest.db_info
........\..\freqtest.fit.qmsg
........\..\freqtest.frm.hdb
........\..\freqtest.hier_info
........\..\freqtest.hif
........\..\freqtest.icc
........\..\freqtest.map.cdb
........\..\freqtest.map.hdb
........\..\freqtest.map.qmsg
........\..\freqtest.pre_map.hdb
........\..\freqtest.project.hdb
........\..\freqtest.rpp.qmsg
........\..\freqtest.rtlv.hdb
........\..\freqtest.rtlv_sg.cdb
........\..\freqtest.rtlv_sg_swap.cdb
........\..\freqtest.sgate.rvd
........\..\freqtest.sgdiff.cdb
........\..\freqtest.sgdiff.hdb
........\..\freqtest.signalprobe.cdb
........\..\freqtest.sim.hdb
........\..\freqtest.sim.qmsg
........\..\freqtest.sim.rdb
........\..\freqtest.sim.vwf
........\..\freqtest.sld_design_entry.sci
........\..\freqtest.sld_design_entry_dsc.sci
........\..\freqtest.swb.qmsg
........\..\freqtest.syn_hier_info
........\..\freqtest.tan.qmsg
........\..\freqtest_cmp.qrpt
........\..\freqtest_sim.qrpt
........\freqtest.asm.rpt
........\freqtest.cdf
........\freqtest.done
........\freqtest.fit.eqn
........\freqtest.fit.rpt
........\freqtest.fit.summary
........\freqtest.flow.rpt
........\freqtest.map.eqn
........\freqtest.map.rpt
........\freqtest.map.summary
........\freqtest.pin
........\freqtest.pof
........\freqtest.qpf
........\freqtest.qsf
........\freqtest.qws
........\freqtest.sim.rpt
........\freqtest.sof
........\freqtest.tan.rpt
........\freqtest.tan.summary
........\freqtest.vhd
........\freqtest.vwf
........\ftctrl.vhd
........\gate_clk.vhd
........\reg32b.vhd
........\sim.cfg

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