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lab10_design_files

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  • Update : 2018-05-12
  • Size : 10kb
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Lab10 design files in Verilog
Packet file list
(Preview for download)
FilenameSizeUpdate
Verilog_design_files 0 2012-08-30
Verilog_design_files\Lab10_Part1.v 3387 2012-08-30
Verilog_design_files\Lab10_Part2.v 2847 2012-08-30
Verilog_design_files\Peripheral_on_External_Bus.v 2474 2012-08-30
Verilog_design_files\READ_ME.txt 156 2012-08-30
Verilog_design_files\Seven_Segment_Display.v 3060 2012-08-30
Verilog_design_files\SRAM_Controller.v 2430 2012-08-30
Verilog_design_files\part1 0 2011-02-18
Verilog_design_files\part1\DE1 0 2012-08-30
Verilog_design_files\part1\DE2 and DE2-115 0 2012-08-30
Verilog_design_files\part2 0 2012-08-30
VHDL_design_files 0 2012-08-30
VHDL_design_files\Lab10_Part1.vhd 7282 2012-08-30
VHDL_design_files\Lab10_Part2.vhd 5231 2012-08-30
VHDL_design_files\Peripheral_on_External_Bus.vhd 3215 2012-08-30
VHDL_design_files\READ_ME.txt 156 2012-08-30
VHDL_design_files\Seven_Segment_Display.vhd 3345 2012-08-30
VHDL_design_files\SRAM_Controller.vhd 2727 2012-08-30
VHDL_design_files\part1 0 2011-02-18
VHDL_design_files\part1\DE1 0 2012-08-30
VHDL_design_files\part1\DE2 and DE2-115 0 2012-08-30
VHDL_design_files\part2 0 2012-08-30
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