Based on the srt-2 algorithm, the use of Verilog to achieve 16-bit unsigned fixed-point divider number (divisor, dividend by 16-bit integer and 16 fractional composition operators from 32-bit integer and 16 fractional composition, the remainder by 32 small array into)

Packet : 5956447divider.rar filelist
divider\divider.v
divider\div_ctl.v
divider\div_datapath.v
divider\div_tb.v
divider\read me.txt
divider

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